1. Field of the Invention
The present invention generally relates to data processing techniques and, in particular, to a system and method for writing data to a register included within a register file. The present invention is particularly advantageous in applications that maintain a single bit of data in each register of the register file.
2. Related Art
Predication techniques have been developed to increase the performance of many instruction processing systems. In this regard, it is well known that each instruction of a computer program is not necessarily executed during each run of the computer program. For example, certain portions of the computer program may execute only if certain run time conditions are true. However, it is generally more efficient for an instruction processing system to begin processing instructions before it is known whether or not the instructions should execute, and predication techniques enable such processing to occur.
In this regard, predicate data is maintained within a processing system. The predicate data indicates whether or not the instructions being processed by the processing system should be executed based on the most recent information available. The predicate data is updated as the instructions are processed by the pipelines of the processing system. If the predicate data indicates that an instruction should not be executed, then the instruction passes without execution through the pipelines. If the predicate data indicates that the instruction should be executed, then the instruction is executed by one of the pipelines. Since processing of the instructions by the pipelines is commenced prior to determinations of whether or not the instructions should execute, the instructions, as a whole, are usually processed by the pipelines quicker.
The predicate data is typically maintained in a predicate register file. The predicate register file usually includes a plurality of predicate registers, in which one bit of information is stored in each register. Each instruction of a computer program is associated with one of the predicate registers in the predicate register file, and more than one instruction may be associated with the same predicate register. In this regard, each instruction usually includes a register identifier that identifies the predicate register associated with the instruction. While the instruction is being processed by one of the pipelines of the processing system, the bit of information in the predicate register associated with the instruction indicates, based on presently available information, whether or not the instruction should be executed.
The predicate data is produced by some of the instructions being processed by the pipelines of the processing system. As different instructions are processed, one instruction may cause the predicate value contained in one of the predicate registers to be asserted while another instruction may, at a different time, cause the same predicate value to be deasserted.
When asserted, the predicate value contained in a predicate register indicates hat the instructions associated with the predicate register are presently predicate nabled (i.e., that the instructions should be executed by the pipelines processing the instructions). When deasserted, the predicate value contained in a predicate register indicates that the instructions associated with the predicate register are presently predicate disabled (i.e., that the instructions should pass through the pipelines without executing).
While an instruction is being processed by one of the pipelines of the processing system, the bit value in the predicate register associated with the instruction is analyzed. If the bit value is asserted, then the instruction is enabled, and the instruction is, therefore, executed. If the bit value is deasserted, then the instruction is disabled, and the instruction, therefore, passes through the pipeline without executing.
The predicate data stored in the predicate register file can also be used to resolve data hazards. For example, if a data hazard exists between two instructions, then one of the instructions is usually stalled (i.e., temporarily prevented from further processing) until the data hazard is resolved or expired. By analyzing the predicate data in the predicate register file, it is possible to detect that one of the instructions is predicate disabled and, therefore, will not execute. As a result, the stall on the one instruction can either be prevented or removed without risking a data error. Therefore, by analyzing the predicate data in the predicate register file, it is sometimes possible to resolve data hazards and to prevent or reduce stalls.
Needless to say, it is important for the predicate register file to be quickly updated once new predicate data is produced so that the predicate register file contains the most recent predicate data available. Unfortunately, there is a finite amount of delay required to write to and read from the predicate register file. Thus, a heretofore unaddressed need exists in the industry for minimizing the amount of time required to update the predicate register file with newly produced predicate data.
The present invention overcomes the inadequacies and deficiencies of the prior art as discussed hereinbefore. Generally, the present invention provides a system and method for writing data to a register file.
In architecture, the system of the present invention utilizes a plurality of registers and at least one write port coupled to each of the registers. The write port receives a register identifier identifying one of the registers and receives at least a first signal, such as a bit of predicate data or a signal of a set/reset signal pair. The write port transmits the first signal and a decode signal to each of the registers. The write port is configured to assert the decode signal transmitted to the one register identified by the register identifier and to deassert the decode signal transmitted to the other registers. Each of the registers includes a set/reset latch and is configured to receive the first signal and the decode signal transmitted to it from the write port. When the first signal received by the register exhibits a first logical state and the decode signal received by the register is asserted, the register sets its set/reset latch in response to the first signal. When the first signal received by the register exhibits a second logical state and the decode signal received by the register is asserted, the register resets its set/reset latch. If the decode signal received by the register is deasserted, then the register ignores the first signal transmitted to the register from the write port.
In accordance with another feature of the present invention, the write port receives a valid signal along with the first signal and transmits the valid signal to each of the registers. The valid signal is asserted when an instruction that produced the first signal is valid (e.g., predicate enabled) and is deasserted when the instruction is invalid (e.g., predicate disabled). Each of the registers is configured to receive the valid signal and to only set or reset its set/reset latch in response to the first signal and the decode signal when the valid signal is asserted.
The present invention can also be viewed as providing a method for storing data. The method can be broadly conceptualized by the following steps: providing a plurality of registers, each of the registers having a set/reset latch; receiving at least a first signal, such as a predicate bit or a signal of a set/reset signal pair, and a register identifier identifying one of the registers; transmitting the first signal and a decode signal to each of the registers; asserting the decode signal transmitted to the one register in response to the register identifier; deasserting the decode signal transmitted to each of the other registers in response to the register identifier; setting the set/reset latch of the one register based on the asserted decode signal if the first signal received by the one register exhibits a first logical state; and resetting the set/reset latch of the one register based on the asserted decode signal when the first bit received by the one register exhibits a second logical state.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following detailed description, when read in conjunction with the accompanying drawings. It is intended that all such features and advantages be included herein within the scope of the present invention and protected by the claims.